SN74LVC1G86DCKR
Gates and Inverters
Technical Specifications
| Type | Description |
|---|---|
| Supply V | 3.575 V |
| Tpd Ns | 4.0 |
| Logic Family | 74LVC Series |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV |
| Input Logic Level - Low | 700mV~800mV |
| Input Logic Level - High | 1.7V~2V |
| Output Logic Level - High | 1.2V;1.9V;2.4V;2.3V;3.8V |
| Quiescent Current(Iq) | 10uA |
| Type | Description |
|---|---|
| Current - Output High(IOH) | 32mA |
| Current - Output Low(IOL) | 32mA |
| Working Voltage V | 3.575 V |
| Features | Live insertion protection;Local shutdown mode;Rear drive protection |
| Operating Temp | -40°C ~ +125°C |
| Channels | 1.0 |
| Package / Case | SC-70-5 |
Product Introduction
This single 2- input exclusive- OR gate is designed for 1.65- V to 5.5- V VCC operation.
The SN74LVC1G86 device performs the Boolean function Y = A x B or Y = AB(overline) + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial- power- down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoFree Package
- Supports 5- V Vcc Operation
- Inputs Accept Voltages to 5.5 V
- Supports Down Translation to Vcc
- Max tpd of 4 ns at 3.3V
- Low Power Consumption, 10- A Max Icc
- ±24 - mA Output Drive at 3.3V
- Ioff Supports Live Insertion, Partial- PowerDown Mode, and Back- Drive Protection
- Latch- Up Performance Exceeds 100 mA Per JESD 78,Class II
- ESD Protection Exceeds JESD 22 2000- V Human- Body Model (A114- A)
- 200- V Machine Model (A115- A)
- 1000- V Charged- Device Model (C101)
Applications
- - Functions as true/complement element: when one input is LOW, the other input signal passes through uninverted
- when one input is HIGH, the other input signal is inverted at the output - Functions as logic identity element: output is active-LOW when all inputs are at the same logic level - Functions as even-parity element: output is active-LOW when an even number of inputs (0 or 2) are active - Functions as odd-parity element: output is active-HIGH when an odd number of inputs (only 1 of 2 inputs) are active
Datasheet
Alternative Parts
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Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Sourcing Information
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