TMS320C6748EZWTD4
DSP (Digital Signal Processors)
Technical Specifications
| Type | Description |
|---|---|
| Type | Fixed-point / floating-point |
| Operating Temp | -40°C ~ +90°C |
| Features | Hardware MAC acceleration;Zero-overhead loop;Parallel data channel;DMA data transfer;High-speed peripheral interface;Integrated PWM control;Interrupt response;Secure storage and protection;Low-power mode;RTC and timer |
| Type | Description |
|---|---|
| Clock Rate | 456MHz |
| Package / Case | NFBGA-361 |
Product Introduction
The TMS320C6748 fixed- and floating-point DSP is a low-power applications processor based on the C674x DSP core. This DSP consumes significantly less power compared to other TMS320C6000™ platform DSPs.
This device enables OEMs and ODMs to leverage the flexibility of a fully integrated mixed-processor solution, accelerating time-to-market for products that combine a robust OS, rich user interface, and high processor performance.
The DSP core employs a 2-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct-mapped cache, and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) contains 256KB of memory space shared between program and data spaces. L2 memory is configurable as mapped memory, cache, or a combination of both. Although other masters in the system can access DSP L2, an additional 128KB of shared RAM is provided for other masters to use, avoiding impact on DSP performance.
For devices with security features, TI's Basic Secure Boot protects user IP and prevents external entities from modifying user-developed algorithms. The secure boot process begins from a hardware-based "root of trust," ensuring code execution starts from a known secure location. The JTAG port is locked by default to prevent emulation and debug attacks; however, it can be enabled during secure boot in application development. Boot modules stored in external non-volatile memory (e.g., flash or EEPROM) are encrypted at rest and are decrypted and authenticated when loaded during secure boot. The encryption and decryption process protects customer IP, enabling customers to securely configure the system and start the device with known trusted code.
Basic Secure Boot uses SHA-1 or SHA-256 and AES-128 for boot image authentication. Additionally, Basic Secure Boot uses AES-128 for boot image encryption. The secure boot process employs a multi-layer encryption mechanism that not only protects the boot process but also enables secure upgrades of boot and application software code. The device uses one 128-bit device-specific key to protect the customer key; this 128-bit key is generated by a NIST-800-22 certified random number generator and is known only to that device. When an update is required, the customer can use the key to create a new encrypted image. The device can then retrieve this image via an external interface (e.g., Ethernet) and overwrite the existing code.
The peripheral set includes: one 10Mbps/100Mbps Ethernet Media Access Controller (EMAC) with Management Data Input/Output (MDIO) module; one USB 2.0 OTG interface; one USB 1.1 OHCI interface; two I2C bus interfaces; one multi-channel audio serial port (McASP) with 16 serializers and FIFO buffers; two multi-channel buffered serial ports (McBSP) with FIFO buffers; two serial peripheral interfaces (SPI) supporting multiple chip selects; four configurable 64-bit general-purpose timers (one configurable as watchdog); one configurable 16-bit host port interface (HPI); up to nine banks of GPIO pins (each bank containing 16 pins, each supporting programmable interrupt and event generation modes and multiplexing with other peripherals); three UART interfaces (all supporting RTS and CTS); two enhanced high-resolution PWM (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals (configurable as three capture inputs or three APWM outputs); and two external memory interfaces (one asynchronous SDRAM External Memory Interface (EMIFA) for slow memory or peripherals, and one high-speed DDR2/Mobile DDR controller).
The EMAC provides an efficient interface between the device and the network. The EMAC supports 10Base-T and 100Base-TX, or 10Mbps and 100Mbps, in both half-duplex and full-duplex modes. Additionally, the device provides an MDIO interface for PHY configuration. The EMAC supports MII and RMII interfaces.
Features
- 375MHz and 456MHz C674x fixed- and floating-point VLIW DSP
- C674x instruction set features
- Superset of C67x+ and C64x+ ISA
- Up to 3648 MIPS and 2746 MFLOPS
- Byte-addressable (8-bit, 16-bit, 32-bit, and 64-bit data)
- 8-bit overflow protection
- Bit-field extract, set, clear
- Normalization, saturation, bit counting
- Compact 16-bit instructions
- C674x two-level cache architecture
- 32KB L1P program RAM/cache
- 32KB L1D data RAM/cache
- 256KB L2 unified mapped RAM/cache
- Flexible RAM/cache partitioning (L1 and L2)
- Enhanced Direct Memory Access Controller 3 (EDMA3)
- 2 channel controllers
- 3 transfer controllers
- 64 independent DMA channels
- 16 quick DMA channels
- Programmable transfer burst size
- TMS320C674x floating-point VLIW DSP core
- Load-store architecture with unaligned support
- 64 general-purpose registers (32-bit)
- 6 ALU (32-bit and 40-bit) functional units
- Supports 32-bit integer, SP (IEEE single-precision/32-bit), and DP (IEEE double-precision/64-bit) floating-point
- Up to 4 SP additions per clock; up to 4 DP additions per 2 clocks
- Up to 2 floating-point (SP or DP) reciprocal approximation (RCPxP) and reciprocal square root approximation (RSQRxP) operations per cycle
- 2 multiply functional units
- Mixed-precision IEEE floating-point multiply supports up to:
- 2 SP × SP → SP operations per clock
- 2 SP × SP → DP operations per 2 clocks
- 2 SP × DP → DP operations per 3 clocks
- 2 DP × DP → DP operations per 4 clocks
- Fixed-point multiply supports 2 32×32-bit, 4 16×16-bit, or 8 8×8-bit multiplications per clock cycle, with complex multiply support
- Instruction compression for reduced code size
- Conditions supported for all instructions
- Hardware support for modulo loop operation
- Protected mode operation
- Additional support for error detection and program redirection
- Software support
- TI DSP BIOS
- Chip support library and DSP library
- 128KB shared RAM memory
- 1.8V or 3.3V LVCMOS I/O (except USB and DDR2 interfaces)
- 2 external memory interfaces
- EMIFA
- NOR (8-bit or 16-bit wide data)
- NAND (8-bit or 16-bit wide data)
- 16-bit SDRAM with 128MB address space
- DDR2/Mobile DDR memory controller with two options:
- 16-bit DDR2 SDRAM with 256MB address space
- 16-bit mDDR SDRAM with 256MB address space
- 3 configurable 16550-type UART modules
- With modem control signals
- 16-byte FIFO
- 16x or 13x oversampling options
- LCD controller
- 2 SPI interfaces, each with multiple chip selects
- 2 MMC/SD card interfaces with SDIO
- 2 master/slave I²C Bus
- 1 HPI with high bandwidth via 16-bit multiplexed address and data bus
- Programmable Real-Time Unit Subsystem (PRUSS)
- 2 independent PRU cores
- 32-bit load-store RISC architecture
- 4KB instruction RAM per core
- 512-byte data RAM per core
- PRUSS can be disabled via software for power saving
- Register 30 of each PRU exported from subsystem in addition to normal R31 output of PRU core
- Standard power management mechanisms
- Clock gating
- Complete subsystem under a single PSC clock gating domain
- Dedicated interrupt controller
- Dedicated switchboard source
- USB 1.1 OHCI (host) with integrated PHY (USB1)
- USB 2.0 OTG port with integrated PHY (USB0)
- USB 2.0 high-speed and full-speed client
- USB 2.0 high-speed, full-speed, and low-speed host
- Endpoint 0 (control)
- Endpoints 1, 2, 3, and 4 (control, bulk, interrupt, or ISOC) RX and TX
- 1 McASP
- 2 clock zones and 16 serial data pins
- Supports TDM, I2S, and similar formats
- Supports DIT
- FIFO buffers for transmit and receive
- 2 McBSP
- Supports TDM, I2S, and similar formats
- AC97 audio codec interface
- Telecom interface (ST-Bus, H100)
- 128-channel TDM
- FIFO buffers for transmit and receive
- 10/100Mbps Ethernet MAC (EMAC)
- IEEE 802.3 compliant
- MII
- RMII
- MDIO module
- Video Port Interface (VPIF)
- 2 8-bit SD (BT.656), single 16-bit, or single raw (8-bit, 10-bit, and 12-bit) video capture channels
- 2 8-bit SD (BT.656), single 16-bit video display channels
- Universal Parallel Port (uPP)
- High-speed parallel interface to FPGAs and data converters
- Two channels with data width from 8-bit to 16-bit (inclusive)
- Single data rate or double data rate transfer
- Supports multiple interfaces with START, ENABLE, and WAIT control
- SATA controller
- Supports SATA I (1.5Gbps) and SATA II (3.0Gbps)
- Full SATA power management feature support
- Up to 32 hardware-assisted Native Command Queuing (NCQ)
- Supports port multiplier and command-based switching
- RTC with 32kHz oscillator and independent power rail
- 3 64-bit general-purpose timers (each configurable as two 32-bit timers)
- 1 64-bit general-purpose or watchdog timer (configurable as two 32-bit timers)
- 2 eHRPWM
- Dedicated 16-bit time-base counter with period and frequency control
- 6 single-edge outputs, 6 dual-edge symmetric outputs, or 3 dual-edge asymmetric outputs
- Dead-band generation
- PWM chopping via high-frequency carrier
- Trip-zone inputs
- 3 32-bit eCAP modules
- Configurable as 3 capture inputs or 3 APWM outputs
- Single-shot capture of up to 4 event timestamps
- Commercial, extended, or industrial temperature
Applications
- - Banknote verification - Biometric recognition - Machine vision (low-end)
Datasheet
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | 3A991A2 |
| Type | Details |
|---|---|
| CNHTS | 8542319090 |
Sourcing Information
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