TMS320C6713BPYP200

Technical Specifications

Product Introduction

Features

• Eight 32-Bit Instructions/Cycle
• 32/64-Bit Data Word
• 300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
• 3.3-, 4.4-, 5-, 6-lnstruction Cycle Times
• 2400/1800,1800/1350,1600/1200,and 1336/1000MIPS/MFLOPS
• Rich Peripheral Set, Optimized for Audio
• Highly Optimized c/c++ Compiler
• Extended Temperature Devices Available
• Advanced Very Long Instruction Word (VLIW) TMS320C67xTM DSP Core
• Eight Independent Functional Units: 2 ALUs (Fixed-Point), 4 ALUs (Floating-/Fixed-Point), 2 Multipliers (Floating-/Fixed-Point)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Instruction Set Features: Native Instructions for IEEE 754 - Single- and Double-Precision, Byte-Addressable (8-, 16-, 32-Bit Data), 8-Bit Overflow Protection, Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
• L1/L2 Memory Architecture: 4K-Byte L1P Program Cache (Direct-Mapped), 4K-Byte L1D Data Cache (2-Way), 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM
• Device Configuration: Boot Mode: HPl, 8-, 16-, 32-Bit ROM Boot, Endianness: Little Endian, Big Endian
• 32-Bit External Memory Interface (EMIF): Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM, 512M-Byte Total Addressable External Memory Space
• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• 16-Bit Host-Port Interface (HPl)
• Two McASPs: Two Independent Clock Zones Each (1 TX and 1 RX), Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones, Each Clock Zone Includes: Programmable Clock Generator, Programmable Frame Sync Generator, TDM Streams From 2-32 Time Slots, Support for Slot Size: 8,12,16, 20,24, 28,32 Bits, Data Formatter for Bit Manipulation, Wide Variety of I2S and Similar Bit Stream Formats, Integrated Digital Audio Interface Transmitter (DIT) Supports: S/PDIF, IEC60958-1,AES-3, CP-430 Formats, Up to 16 transmit pins, Enhanced Channel Status/User Data, Extensive Error Checking and Recovery
• Two Inter-lntegrated Circuit Bus (I2c BusTM) Multi-Master and Slave Interfaces
• Two Multichannel Buffered Serial Ports: Serial-Peripheral-Interface (SPI), High-Speed TDM Interface, AC97 Interface
• Two 32-Bit General-Purpose Timers
• Dedicated GPIO Module With 16 pins (External Interrupt Capable)
• Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
• IEEE-1149.1 (JTAGt) Boundary-Scan-Compatible
• 208-Pin PowerPADTM PQFP (PYP)
• 272-BGA Packages (GDP and ZDP)
• 0.13-μm/6-Level Copper Metal Process
• CMos Technology
• 3.3-V I/Os, 1.2+-V Internal (GDP/ZDP/ PYP)
• 3.3-V I/Os, 1.4-V Internal(GDP/ZDP) [300 MHz]

Datasheet

Compliance & Export Codes