TLV320AIC3204IRHBR

The TLV320AIC3204 (also called the AIC3204) is a flexible, low-power, low-voltage stereo audio codec with programmable inputs and outputs, PowerTune capabilities, fixed predefined and parameterizable signal-processing blocks, integrated PLL, integrated LDOs and flexible digital interfaces.

The TLV320AIC3204 includes extensive register-based control of power, input/output channel configuration, gains, effects, pin-multiplexing and clocks, allowing precise targeting of the device to its application. Combined with the advanced PowerTune technology, the device covers operations from 8 kHz mono voice playback to audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications.

The record path of the TLV320AIC3204 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations covering single-ended and differential setups, as well as floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by mechanical coupling, e.g. optical zooming in a digital camera.

The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC and analog input signals as well as programmable volume controls. The playback path contains two high-power output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways, including stereo and mono BTL.

The integrated PowerTune technology allows the device to be tuned to an optimum power-performance trade-off. Mobile applications frequently have multiple use cases requiring very low power operation while being used in a mobile environment. When used in a docked environment power consumption typically is less of a concern, while minimizing noise is important. With PowerTune, the TLV320AIC3204 addresses both cases.

The voltage supply range for the TLV320AIC3204 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, integrated LDOs generate the appropriate analog or digital supply from input voltages ranging from 1.8V to 3.6V. The device supports digital I/O voltages in the range of 1.1V–3.6V.

The required internal clock of the TLV320AIC3204 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable clock signal, PLL use is not recommended for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.

The device is available in the 5-mm×5-mm, 32-pin QFN package.