SN74LVC2G86DCUR
Gates and Inverters
Technical Specifications
| Type | Description |
|---|---|
| Supply V | 3.575 V |
| Tpd Ns | 4.7 |
| Logic Family | 74LVC |
| Output Logic Level - Low | 450mV;300mV;400mV;550mV |
| Input Logic Level - Low | 700mV;800mV |
| Input Logic Level - High | 1.7V;2V |
| Output Logic Level - High | 1.2V;1.9V;2.4V;2.3V;3.8V |
| Quiescent Current(Iq) | 10uA |
| Type | Description |
|---|---|
| Current - Output High(IOH) | 32mA |
| Current - Output Low(IOL) | 32mA |
| Working Voltage V | 3.575 V |
| Features | Live insertion protection;Local shutdown mode;Rear drive protection |
| Operating Temp | -40°C ~ +125°C |
| Channels | 2.0 |
| Package / Case | VSSOP-8 |
Product Introduction
Available in the NanoFree™ Package
Supports 5-V Vcc Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.7 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25℃
Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3V, TA = 25℃
Ioff Supports Live Insertion, Partial-Power Down Mode and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-VCC operation.
The SN74LVC2G86 performs the Boolean function Y = A⊕B or Y = A(overline)B + A(overline)B(overline) in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in NanoFree package
- 5V supply voltage operation supported
- Inputs tolerant up to 5.5V
- Maximum propagation delay tpd of 4.7ns at 3.3V supply
- Low power consumption, maximum supply current ICC of 10μA
- Output drive capability of ±24mA at 3.3V supply
- Typical output ground bounce VOLP less than 0.8V at VCC=3.3V, TA=25℃
- Typical output high undershoot VOHV greater than 2V at VCC=3.3V, TA=25℃
- Ioff supports hot insertion, partial power-down mode, and back-drive protection
- Latch-up performance exceeds 100mA per JESD 78 Class II
- ESD protection per JESD 22: HBM 2000V, MM 200V, CDM 1000V
Applications
- - Functions as a true/complement element: when one input is LOW, the other input signal is reproduced in its original form at the output
- when one input is HIGH, the other input signal is reproduced in inverted form at the output - Functions as a logic identity element: output is active LOW when all inputs are at the same logic level - Functions as an even-parity element: output is active LOW when an even number of inputs are active - Functions as an odd-parity element: output is active HIGH when an odd number of inputs are active
Datasheet
Alternative Parts
Common SN74LVC2G86DCUR alternatives overseas buyers search for:
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Sourcing Information
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