SN74LVC1G32DBVR
Gates and Inverters
Technical Specifications
| Type | Description |
|---|---|
| Supply V | 3.575 V |
| Tpd Ns | 4.0 |
| Input Logic Level - Low | - |
| Input Logic Level - High | 1.7V~2V |
| Logic Family | 74LVC Series |
| Output Logic Level - High | 1.2V;1.9V;2.4V;3.8V |
| Quiescent Current(Iq) | 10uA |
| Current - Output High(IOH) | 32mA |
| Type | Description |
|---|---|
| Output Logic Level - Low | 450mV;300mV;400mV;550mV |
| Current - Output Low(IOL) | 32mA |
| Features | Local shutdown mode |
| Operating Temp | -40°C ~ +85°C |
| Working Voltage V | 3.575 V |
| Channels | 1.0 |
| Package / Case | SOT-23-5 |
Product Introduction
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G32 performs the Boolean function Υ = A + B or Υ = A(overline) • B(overline)(overline) in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoStar and NanoFree Packages
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 3.6 ns at 3.3 V
- Low Power Consumption, 10-μA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Datasheet
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Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Sourcing Information
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