PIC18F26K83-I/SS

Technical Specifications

Product Introduction

Features

• C Compiler Optimized RISC Architecture
• Operating Speed:
• Up to 64 MHz clock operation
• 62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
• Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
• User-programmable source and destination sizes
• Hardware and software-triggered data transfers
• System Bus Arbiter with User-Configurable Priorities for Scanner and DMA1/DMA2 with respect to the main line and interrupt execution
• Vectored Interrupt Capability:
• Selectable high/low priority
• Fixed interrupt latency
• Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
• Variable prescaler selection
• Variable window size selection
• Configurable in hardware or software
• Up to 64 KB Flash Program Memory
• Up to 4 KB Data SRAM Memory
• Up to 1 KB Data EEPROM
• Memory Access Partition (MAP):
• Configurable boot and app region sizes with individual write-protections
• Programmable Code Protection
• Device Information Area (DIA) stores:
• Unique IDs and Device IDs
• Temp Sensor factory-calibrated data
• Fixed Voltage Reference calibrated data
• Device Configuration Information (DCI) stores:
• Erase row size
• Number of write latches per row
• Number of user rows
• Data EEPROM memory size
• Pin count
• Operating Voltage Range:
• 1.8V to 3.6V (PIC18LF25/26K83)
• 2.3V to 5.5V (PIC18F25/26K83)
• Temperature Range:
• Industrial: -40℃ to 85℃
• Extended: -40℃ to 125℃
• DOZE mode: Ability to run CPU core slower than the system clock
• IDLE mode: Ability to halt CPU core while internal peripherals continue operating
• SLEEP mode: Lowest power consumption
• Peripheral Module Disable (PMD):
• Ability to disable unused peripherals to minimize power consumption
• Sleep mode: 60 nA @1.8V, typical
• Windowed Watchdog Timer: 720 nA @ 1.8V, typical
• Secondary Oscillator: 580 nA @ 32 kHz
• Operating Current:
• 4 uA @ 32 kHz, 1.8V, typical
• 45 uA/MHz @ 1.8V, typical
• Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT):
• Hardware monitoring and Fault detection
• Four 16-Bit Timers (TMR0/1/3/5)
• Four Configurable Logic Cell (CLC):
• Integrated combinational and sequential logic
• Three Complementary Waveform Generators (CWGs):
• Rising and falling edge dead-band control
• Full-bridge, half-bridge, 1-channel drive
• Multiple signal sources
• Programmable dead band
• Fault-shutdown input
• Four Capture/Compare/PWM (CCP) modules
• Four 10-bit Pulse-Width Modulators (PWMs)
• Numerically Controlled Oscillator (NCO):
• Generates true linear frequency control
• High resolution using 20-bit accumulator and 20-bit increment values
• DSM: Data Signal Modulator:
• Multiplex two carrier clocks, with glitch prevention feature
• Multiple sources for each carrier
• Programmable CRC with Memory Scan:
• Reliable data/program memory monitoring for fail-safe operation (e.g., Class B)
• Calculate CRC over any portion of program memory
• Two UART Modules:
• Modules are Asynchronous, RS-232, RS-485 compatibility.
• One of the UART modules supports LIN Master and Slave, DMX mode, DALI Gear and Device protocols
• Automatic and user-timed BREAK period generation
• DMA Compatible
• Automatic checksums
• Programmable 1, 1.5, and two Stop bits
• Wake-up on BREAK reception
• One SPI module:
• Configurable length bytes
• Configurable length data packets
• Receive-without-transmit option
• Transmit-without-receive option
• Transfer byte counter
• Separate Transmit and Receive Buffers with 2-byte FIFO and DMA capabilities
• CAN module:
• Conforms to CAN 2.0B Active Specification
• Three operating modes: Legacy (compatible with existing PIC18CXX8/FXX8 CAN modules), Enhanced mode, and FIFO mode.
• Message bit rates up to 1 Mbps
• DeviceNet data byte filter support
• Six programmable receive/transmit buffers
• Three dedicated transmit buffers
• Two dedicated receive buffers
• 16 Full, 29-bit acceptance filters with dynamic association
• Three full, 29-bit acceptance masks
• Automatic remote frame handling
• Advanced error management features.
• Two I²C modules, SMBus, PMBus compatible:
• Dedicated Address, Transmit and Receive buffers
• Bus Collision Detection with arbitration
• Bus time-out detection and handling
• Multi-Master mode
• Separate Transmit and Receive Buffers with 2-byte FIFO and DMA capabilities
• I²C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections
• Device I/O Port Features:
• 25 I/O pins (PIC18(L)F25K83)
• One input-only pin
• Individually programmable I/O direction, open-drain, slew rate, weak pull-up control
• Interrupt-on-change
• Three External Interrupt Pins
• Peripheral Pin Select (PPS):
• Enables pin mapping of digital I/O

Applications

• - automotive - industrial

Datasheet

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Compliance & Export Codes