PCM5100AQPWRQ1

The PCM510xA-Q1 is a family of monolithic CMOS ICs featuring a stereo DAC and additional support circuitry in a TSSOP package. The latest-generation advanced segmented DAC architecture delivers superior dynamic performance with enhanced tolerance to clock jitter.

The PCM510xA-Q1 provides a 2.1-VRMS ground-centered output, allowing designers to eliminate DC-blocking capacitors at the output as well as the external muting circuitry traditionally associated with single-supply line drivers.

The integrated line driver outperforms all other charge-pump-based line drivers by supporting loads as low as 1 kΩ. With this capability, the PCM510xA-Q1 can effectively drive up to 10 units in parallel.

The on-chip integrated PLL eliminates the need for a system clock (commonly referred to as a master clock), enabling 3-wire I²S connectivity and reducing system EMI.

Intelligent clock error detection and PowerSense undervoltage protection deliver pop-free performance through a two-stage muting system. Upon a clock error or system power failure, the device applies digital attenuation to the data (or the last known good data) before muting the analog circuitry.

Compared to conventional DAC technology, the PCM510xA-Q1 family offers out-of-band noise as low as 20 dB — measured from the traditional 100 kHz OBN reference all the way to 3 MHz — reducing EMI and aliasing in downstream amplifiers and ADCs.

The PCM510xA-Q1 accepts industry-standard audio data formats with 16 to 32 bits of data, supporting sample rates up to 384 kHz.