LPC2468FBD208K
Microcontrollers (MCU/MPU)
Technical Specifications
| Type | Description |
|---|---|
| Core Processor | - |
| Core Size | 16 bit |
| Maximum Clock Speed | 72 MHz |
| Program Storage Size | 512 KB |
| Number of I/O | 160 |
| Flash Type | FLASH |
| ADC (Bit) | 10 bit |
| Type | Description |
|---|---|
| Oscillator Type | Built-in |
| EEPROM | - |
| DAC (Bit) | 10 bit |
| Operating Temperature | -40°C~+85°C |
| Supply Voltage | 3V~3.6V |
| Package / Case | LQFP-208(28x28) |
Product Introduction
The LPC2468 microcontroller is designed around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. It has 512 kB of on-chip high-speed flash memory with a special 128-bit wide memory interface and accelerator architecture, enabling the CPU to execute sequential instructions from flash memory at the maximum 72 MHz system clock rate. It can execute both 32-bit ARM and 16-bit Thumb instructions.
The LPC2468 is ideal for multi-purpose communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed Device/Host/OTG Controller, four UARTs, two CAN channels, an SPI interface, two SSPs, three I2C interfaces, and an I2S interface. It also has an on-chip 4 MHz internal precision oscillator, 98 kB of total RAM, and an External Memory Controller (EMC). These features make it optimally suited for communication gateways and protocol converters.
Complementing the serial communication controllers, clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO lines. The LPC2468 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC), allowing external inputs to generate edge-triggered interrupts. All of these features make it particularly suitable for industrial control and medical systems.
Features
- ARM7TDMI-S processor, running at up to 72 MHz
- 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access
- 98 kB on-chip SRAM includes: 64 kB of SRAM on the ARM local bus for high performance CPU access; 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM; 16 kB SRAM for general purpose DMA use also accessible by the USB; 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain
- Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention
- EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM
- Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts
- General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP, I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers
- Serial Interfaces: Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB; USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller; Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO; CAN controller with two channels; SPI controller; Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller; Three I2C-bus interfaces (one with open-drain and two with standard port pins); I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA
- Other peripherals: SD/MMC memory card interface; 160 General purpose I/O pins with configurable pull-up/down resistors; 10-bit ADC with input multiplexing among 8 pins; 10-bit DAC; Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input; Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs; RTC with separate power domain. Clock source can be the RTC oscillator or the APB clock; 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off; WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock
- Standard ARM test/debug interface for compatibility with existing tools
- Emulation trace module supports real-time trace
- Single 3.3 V power supply (3.0 V to 3.6 V)
- Four reduced power modes: idle, sleep, power-down, and deep power-down
- Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources
- Processor wake-up from Power-down mode via any interrupt
Applications
- Multi-purpose communication applications
- Communication gateways
- Protocol converters
- Industrial control
- Medical systems
Datasheet
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | 3A991A2 |
| Type | Details |
|---|---|
| CNHTS | 8542319090 |
Sourcing Information
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