FLXC2002G-26

This mobile low-power DDR4 SDRAM is a high-speed CMOS dynamic random access memory, internally configured as a single-channel or dual-channel device. Each channel contains 16 DQ signals and 8 banks. The device employs a 2-cycle, single data rate protocol on the CA bus to reduce the number of input signals in the system. "2-cycle" means that the command/address is decoded across two transactions, such that half of the command/address information is captured on each of two consecutive CK rising edges. The 6-bit CA bus carries command, address, and bank information. Certain commands — such as Read, Write, Masked Write, and Activate — require two consecutive 2-cycle single data rate commands to complete the instruction. The device employs a double data rate protocol on the DQ bus for high-speed operation. The double data rate interface transfers two data bits per DQ per clock cycle and is matched to a 16n prefetch DRAM architecture. A single write/read access consists of a 16n-bit wide data transfer to or from the DRAM core, along with 16 corresponding n-bit wide data transfers at the I/O pins.