DSPIC33EP64GS506-I/PT

Technical Specifications

Product Introduction

Features

• Operating conditions: 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS; 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
• Flash architecture: Dual-partition flash program memory with live update support (64-Kbyte devices), runtime programming, partition soft-swap
• Core: 16-bit dsPIC33E CPU, code-efficient (C and assembly) architecture, two 40-bit wide accumulators, single-cycle (MAC/MPY) dual data fetch, single-cycle mixed-sign multiply-accumulate with hardware divide, 32-bit multiply support, two additional working register banks (reduced context switching)
• Clock management: ±0.9% internal oscillator, programmable PLL and oscillator clock sources, Fail-Safe Clock Monitor (FSCM), independent Watchdog Timer (WDT), fast wake-up and start-up
• Power management: Low-power management modes (Sleep, Idle, Doze), integrated Power-on Reset and Brown-out Reset, 0.5 mA/MHz dynamic current (typical), 10 μA IPD current (typical)
• High-speed PWM: Five PWM generators (two outputs per generator), independent time base and duty cycle per PWM, 1.04 ns PWM resolution (frequency, duty cycle, dead time, and phase), center-aligned, redundant, complementary, and true independent output modes, independent fault and current-limit inputs, output override control, supports AC/DC, DC/DC, inverter, PFC, and lighting applications
• Advanced analog features: High-speed ADC module, 12-bit, four dedicated SAR ADC cores and one shared SAR ADC core, configurable resolution per ADC core (up to 12-bit), up to 3.25 Msps conversion rate per channel at 12-bit resolution, 12 to 22 single-ended inputs, dedicated result buffer per analog channel, flexible independent ADC trigger sources, two digital comparators, two oversampling filters for enhanced resolution, four rail-to-rail comparators with hysteresis, dedicated 12-bit DAC per analog comparator, up to two DAC reference outputs, up to two external reference inputs, two Programmable Gain Amplifiers (PGA), single-ended or independent ground reference, five selectable gains (4x, 8x, 16x, 32x, and 64x), 40 MHz gain-bandwidth product
• Interconnected SMPS peripherals: Reduced CPU interaction for improved performance, flexible PWM trigger options for ADC conversion, high-speed comparator PWM truncation (typical 15 ns), cycle-by-cycle current-mode control support, current reset mode (variable frequency)
• Timers/Output Compare/Input Capture: Five 16-bit and up to two 32-bit timers/counters, four Output Compare (OC) modules configurable as timer/counters, four Input Capture (IC) modules
• Communication interfaces: Two UART modules (15 Mbps) with LIN/J2602 and IrDA support, two 4-wire SPI modules (15 Mbps), two I²C modules (up to 1 Mbaud) with SMBus support
• Qualification and Class B support: AEC-Q100 REVG (Grade 1, -40°C to +125°C), Class B safety library, IEC 60730, 6×6×0.5 mm UQFN package designed and optimized to simplify IPC9592B Class II temperature cycling qualification
• I/O: Constant current source (nominal 10 μA), sink/source current up to 12 mA/15 mA respectively, pin-specific standard VOH/VOL, 5V tolerant pins, selectable open-drain pull-up and pull-down, external interrupt on all I/O pins, Peripheral Pin Select (PPS) enabling function remapping via six virtual I/Os
• Debugger development support: In-circuit and in-application programming, five program and three complex data breakpoints, IEEE 1149.2-compliant (JTAG) boundary scan, trace and runtime monitoring

Datasheet

Compliance & Export Codes