AT32F455CET7

Technical Specifications

Product Introduction

Features

• ARM 32-bit Cortex-M4F MCU with 256 KB to 512 KB Flash, sLib, QSPI, SDRAM, 17 timers, 2 ADCs, 23 communication interfaces
• Core: ARM 32-bit Cortex-M4F CPU with FPU, up to 192 MHz operating frequency, memory protection unit, single-cycle multiply and hardware divide, FPU, DSP instruction set
• Memory: 256 KB to 512 KB Flash memory, 26 KB boot code area for bootloader, 4 KB OTP memory, sLib secure library area, 144 KB to 108 KB SRAM, external memory controller with 16-bit data bus supporting SRAM, PSRAM, NOR and SDRAM, QSPI interface for external SPI Flash or SPI RAM
• External memory controller usable as LCD parallel interface, compatible with 8080/6800 modes
• Power control: 2.4V to 3.6V supply, POR/BOR/PVD, low-power modes including Sleep, Deep Sleep and Standby, 6 wake-up pins for Standby mode wake-up, VBAT powers low-speed external oscillator, enhanced RTC and 20 × 32-bit battery-backed registers
• Clock and reset management: 4 to 25 MHz crystal oscillator, built-in factory-trimmed 48 MHz HSI clock with 1% accuracy at 25 °C and 2.5% over -40 °C to +105 °C, automatic clock calibration, 32 kHz crystal oscillator, LSI clock
• Analog: 2 × 12-bit 5.33 MSPS ADCs with up to 16 external input channels, configurable resolution 12/10/8/6-bit, hardware oversampling up to 16-bit resolution, temperature sensor, internal reference voltage, VBAT monitoring, 2 × 12-bit DACs
• DMA: 2 × 7-channel DMA controllers (14 channels total) with full flexible mapping
• Up to 117 fast GPIO ports, all mappable to 16 external interrupts, most 5V-tolerant
• Up to 17 timers: 2 × 16-bit 8-channel advanced timers with complementary PWM output, dead-time control and emergency brake; up to 8 × 16-bit and 2 × 32-bit general-purpose timers, each with up to 4 channels for input capture/output compare/PWM or pulse counting and incremental encoder input; 2 × 16-bit basic timers; 2 watchdog timers; SysTick 24-bit downcounter
• Enhanced RTC with auto-wakeup, alarm, sub-second precision, hardware calendar and calibration
• Up to 23 communication interfaces: 3 × I2C with SMBus/PMBus support; 8 × USART with master synchronous SPI and modem control, ISO7816, LIN, IrDA and RS485 driver enable, configurable TX/RX pin swap; 4 × SPI, all multiplexable as half-duplex I2S, with I2S2/I2S3 supporting full-duplex and 1 additional independent full-duplex I2S; 3 × CAN each with 1408-byte dedicated buffer; SDIO interface; OTG FS controller with on-chip PHY, 1280-byte dedicated buffer, crystal-less support in device mode; 10/100M Ethernet MAC with dedicated DMA and 4 KB buffer, IEEE 1588 support, MII/RMII interface; IR transmitter
• CRC calculation unit
• 96-bit unique chip ID
• AES hardware accelerator supporting 256/192/128-bit key sizes
• True random number generator
• Debug: SWD and SWO interfaces
• Operating temperature range: -40 °C to +105 °C
• Package types: LQFP144 20 × 20 mm, LQFP100 14 × 14 mm, LQFP64 10 × 10 mm, LQFP48 7 × 7 mm, QFN48 6 × 6 mm

Datasheet

Compliance & Export Codes