A3906SESTR-T

Designed for pulse width modulated (PWM) control of low voltage stepper motors, and single and dual DC motors, the A3906 is capable of output currents up to 1 A per channel and operating voltages from 2.5 to 9 V.

The A3906 has an internal fixed off-time PWM timer that sets a peak current based on the selection of a current sense resistor. An overcurrent output flag is provided that notifies the user when the current in the motor winding reaches the peak current determined by the sense resistor. The fault output does not affect driver operation.

The A3906 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating.

The A3906 is a dual full-bridge low voltage motor driver capable of operating one stepper motor, two DC motors, or one high current DC motor. MOSFET output stages substantially reduce the voltage drop and the power dissipation of the outputs of the A3906, compared to typical drivers with bipolar transistors.

Output current can be regulated by pulse width modulating (PWM) the inputs. In addition supporting external PWM of the driver, the A3906 limits the peak current by internally PWMing the source driver when the current in the winding exceeds the peak current, which is determined by a sense resistor. A fault output notifies the user that peak current was reached. If internal current limiting is not needed, the sense pin should be shorted to ground.

Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout, internal clamp diodes, and crossover current protection.

The A3906 is designed for portable applications, providing a power-off low current sleep mode and an operating voltage of 2.5 to 9 V.

External PWM Output current regulation can be achieved by pulse width modulating the inputs. Slow decay mode is selected by holding one input high while PWMing the other input. Holding one input low and PWMing the other input results in fast decay.

Blanking This function blanks the output of the current sense comparator when the outputs are switched. The comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of the clamp diodes or to switching transients related to the capacitance of the load. The blank time, tBLANK, is approximately 3 μs.

Sleep Mode An active-low control input used to minimize power consumption when the A3906 is not in use. This disables much of the internal circuitry including the output drivers, internal regulator, and charge pump. A logic high allows normal operation. When coming out of sleep mode, wait 1.5 ms before issuing a command, to allow the internal regulator and charge pump to stabilize.

Enable When all logic inputs are pulled to logic low, the outputs of the bridges are disabled. The charge pump and internal circuitry continue to run when the outputs are disabled.

Charge Pump (CP1, CP2, CP3, and CP4) When supply voltages are lower than 3.5 V, the two-stage charge pump triples the input voltage to a maximum of 7 V above the supply. The charge pump is used to create a supply voltage greater than VBB, to drive the source-side DMOS gates. For pumping purposes, a 0.1 μF ceramic capacitor should be connected between CP1 and CP2, and between CP3 and CP4. A 0.1 uF ceramic capacitor is required between VCP and VBB, to act as a reservoir to operate the highside DMOS devices.

Thermal Shutdown The A3906 will disable the outputs if the junction temperature reaches 165 °C. When the junction temperature drops 15 °C, the outputs will be enabled.

Brake Mode When driving DC motors, the A3906 goes into brake mode (turns on both sink drivers) when both of its inputs are high (IN1 and IN2, or IN3 and IN4). There is no protection during braking, so care must be taken to ensure that the peak current during braking does not exceed the absolute maximum current.

Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP. Initially, a diagonal pair of source and sink DMOS outputs are enabled