74LVC08APW,118
Gates and Inverters
Technical Specifications
| Type | Description |
|---|---|
| Supply V | 2.4 V |
| Tpd Ns | 4.1 |
| output type | - |
| Logic Family | 74LVC Series |
| Output Logic Level - Low | 200mV;600mV;650mV;800mV |
| Input Logic Level - Low | 120mV~800mV |
| Input Logic Level - High | 1.08V~2V |
| Output Logic Level - High | 1.2V;1.8V;2.2V;2.4V |
| Quiescent Current(Iq) | 40uA |
| Type | Description |
|---|---|
| Current - Output High(IOH) | 24mA |
| Current - Output Low(IOL) | 24mA |
| Input Type | Schmitt trigger;TTL-compatible CMOS |
| Working Voltage V | 2.4 V |
| Features | Overvoltage-tolerant input |
| Operating Temp | -40°C ~ +125°C |
| Channels | 4.0 |
| Package / Case | TSSOP-14 |
Product Introduction
The 74LVC08A is a quad 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Features
- Overvoltage tolerant inputs to 5.5 V
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Complies with JEDEC standard:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- - Translator for mixed 3.3V and 5V applications
Datasheet
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Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Sourcing Information
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