74HC74PW,118
Flip Flops
Technical Specifications
| Type | Description |
|---|---|
| Output Type | Complementary |
| Working Voltage V | 4 V |
| Iq A | 4e-05 |
| Number of Bits per Element | 1 |
| Synchronous/Asynchronous | Asynchronous |
| Current - Output High(IOH) | 5.2mA |
| Current - Output Low(IOL) | 5.2mA |
| Type | Description |
|---|---|
| Setup Time | 2ns |
| Hold Time | 2ns |
| Trigger Type | Rising Edge |
| Operating Temp | -40°C ~ +125°C |
| Number of Elements | 2.0 |
| Tpd Ns | 37.0 |
| Package / Case | TSSOP-14 |
Product Introduction
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features
- Wide supply voltage range from 2.0 to 6.0 V
- CMOS low power dissipation
- High noise immunity
- Input levels: For 74HC74: CMOS level For 74HCT74: TTL level
- Symmetrical output impedance
- Balanced propagation delays
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Datasheet
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Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Sourcing Information
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